The present invention relates generally to integrated circuit design, and more particularly, to methods and systems for designing and placing decoupling capacitors in an integrated circuit.
Power supply decoupling capacitors (dcaps) are typically connected between two power supply rails in an integrated circuit design. The dcaps provide dynamic decoupling to noise on the power supply rails or grids. By way of example, one or more dcaps can be connected between Vdd and Vss power grids. The decoupling operation stabilizes the power supply, reduces the electro-magnetic interference (EMI) emissions and increases the circuit reliability.
Traditional dcap design and size and location are focused on existing power grids. By way of example, the traditional dcaps are designed to be seated precisely between a pair of Vdd and Vss power grids. The dcaps are placed along a channel formed by the Vdd and Vss power grids. Placing the dcaps along the channel formed by the power grids is referred to as a linear dcap fill. The dcaps are butted together whenever possible. If it is not possible to butt the dcaps together, then the dcaps are separated by a specifically separated, constant space.
FIG. 1 shows a typical design and placement 100 of dcaps over a channel The dcaps 112A-D are placed across the channel 101 formed by the power grid of Vss 102 and Vdd 104. Dcap 112D cannot be butted to dcap 112C due to design object 108 (e.g., a via). Similarly, dcap 112B cannot be butted to dcap 112A due to design object 106. Conversely, dcap 112C is butted up to dcap 112B. Design objects 106 and 108 would electrically short any dcap placed between dcaps 112A and 112B or between dcaps 112C and 112D. Further, the design objects 106 and 108 can also block any dcaps due to a design rule violation (e.g., device spacing limitations). Even though the objects 106 and 108 are relatively small in area as compared to the dcap, the objects still block at least an entire dcap.
In a typical design, the power grid is usually started from metallization layer M2. Each of the dcaps 112A-112D include an insulating layer 118 (e.g., dielectric) separating two conductive layers (e.g. metal layer or diffused region of a layer). The two conductive layers are typically in layers below the metal layer (e.g., M2 layer) containing the power grid. The dcaps 112A-112D connect to the Vss 102 in the M2 power grid through electrical contacts 114A-D. Similarly, the dcaps 112A-112D connect to the Vdd 104 in the M2 power grid through electrical contacts 116A-D. The higher metal the dcap connects to, the more chance a dcap would be blocked by the structures (e.g., objects 106 and 108) one or more of the underlying metal layers.
Unfortunately as integrated circuit density is increased the traditional dcap designs are difficult and inefficient to achieve the desired dcap size and location. Specifically, the dcaps are large enough to be seated between the power grid pair. As the integrated circuit density is increased there are fewer and smaller areas available for the desired dcap size. The linear dcap fill requirement eliminates many other potential areas that do not include the two power grids and therefore do not have a channel required by the linear fill. The dcaps can block the routing channel if the dcaps are placed ahead of the routing. Alternatively, the routed wires may block the channel for filling the dcaps, if the dcap is placed after the routing. One short wire can block a relatively large area.
Different types of circuits are used in different portions or blocks of the integrated circuit (e.g., a control block, a data path block, an I/O block, etc.). Each different block may have different widths between the power grids, as a result, the dcaps cannot be formed at a uniform size or spacing.
In view of the foregoing, there is a need for a more flexible approach to designing and placing dcaps.